Intel was first one dealing with this and is first one to release a CPU using backplane power delivery, so called PowerVia.
We can make comparison to PCBs where “power planes” are normal. In case of a power plane, copper area is huge, having very low resistance, and close to transistors.
In chips upper metal layers are used for power delivery but we deal with traces and vias having some resistance what causes, eg heating. For example, a modern EUV design has something like 20 metal layers for signals and then few giant metal layers for power and pins. Now imagine a via going thru 20 signal layers moving signal traces away.
As substrate is “not used”, it is used to place a power plane on other side and deliver power directly to transistors from bellow. From Intel info, they gained 6% performance increase and 30% drop in resistance.
Do you know where transistors are?
Thin white line in the middle of picture!
This is also a nice picture, before and afte
As said, power traces are upper metal layers and power must be delivered thru lower ones which are also finer, more expensive, and lot of area is lost on power increasing signal traces length.
TSMC will have something very similar with, probably, same results.
On Intel side first usage will be in Intel4 while TSMC planned for A16 process.
Intel first test were in Blue Sky Creek (based on Crestmont) back in 2023. This is nice image showing how PowerVia affected size:
While Intel plans PowerVia in Intel4 which is scheduled for 2024, TSMC plans A16 for 2026 or 2027.
This gives Intel 2 years advantage.
But, we speak Intel and is to be seen
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